Extended Instruction Pipeline

Extended model of Instruction Pipelining . Additionally includes:

ICache

Instruction cache

Renaming / Allocation stage

Mapping between logical and physical registers. Register renaming is used to eliminate Anti dependencies and Output dependencies .

Issue stage

Manages Issue-Queue that contains instructions which are waiting for operands. For In-Order processors, only the first one is checked, while for Out-Of-Order processors all instructions are checked per clock cycle

Commit Stage

Ensures sequential order. Instructions can only commit if older instructions have commited. Also responsible for removing effects of misspredicted speculative computations.