Instruction Set Architecture

Data Types and formats #

Number of operands (0, 1, 2, 3)
Types of operands
1. Immediate operands (part of the instruction)
2. Register operands (content of the register is the operand)
3. Memory operands (content of a memory address is the operand)
Alignment of operands
- Memory operand is aligned at a n-bit boundary if the address is a multiple of n
- Usually memory operands have to be aligned according to their own size
- Can be required by the ISA to only access size-aligned data
-> Needed for cache lines: If cach lines are byte sized and aligned, for a reasonably large , then smaller data will always fit in a cache line if it is also aligned.

Immediate operands (part of the instruction)
Register operands (content of the register is the operand)
Direct (memory address is part of the instruction)
- Only if you know the address of a constant or something in the data segment
Register indirect: (memory address is in a register)
Indexed: (register indirect plus fixed offset)
- Can be used for PC-relative jumps (maybe for jump tables like for switch statements?)

structure of opcode and operands
either single format for all instructions (Von Neumann Architecture )
or more flexible ones (complex decoding)
(NOTE: instruction size depends on operand types (registers really small, memory address much bigger))

Memory in the processor
Fast access (fastest access)
Types:
1. General registers: interges, addesses
2. Floating point registers
3. Special refisters: multimedia, loop control register, …
4. System registers: program counter, status, control register
Only few registers defined by ISA to keep names as short as possible
Register file = set of (same type) registers
Sliding window register file:
- Attempt to have a lot of registers, but still have instuction length short:
  - Have a “Window” you can move over the full register file. All register access then only acts on the active window
  - Special operations to slide the window of addresses over the real registers

Motivation: Applications and data need to be protected from other running programs
OS manages hardware -> Assigns memory ranges to processes
Two execution modes:
1. Supervisor mode:
  - Reserved for OS
  - Full access to all components
    - Can modyfiy virtual address table
2. User mode:
  - Limited access
  - Access to memory only through memory translations (Virtual address space)
  - No priviledged instruction for I/O or accerss to control registers

Exception (Interrupt) triggered by the program
- Executing a priviledged instruction in user mode
- Division by Zero
- Access virtual page with wrong permissions
Exception handled by the OS:
1. Interrupt the currently executed instruction
2. save processor state (all registers and immediate values)
3. jump to handler for the exception
4. switch to supervisor mode
5. handle the exception
6. return to original instruction in user mode

Precise exceptions:
- Assume all previous instructions are complete
- Assume no future instructions have been exectuted
- Assumes no piplining
Imprecise exceptions:
- Exceptions can happen out of order

CISC

Complex instruction set architecture

RISC

Complex instruction set architecture

Comparison - CISC leads to shorter programs - CISC is more flexible - RISC is faster - RISC needs to emulate more complex instuctions