Reducing cache hit time

A Cache Optimization .

• Most important for 1st level cache

• Techniques:

  • Small cache
  • no or low associativity
  • Avoid address translation
  • Way prediction

Parallel vs Serial Tag-Data Array #

• Parallel

  • In one step put in tag and if hit select correct cacheline from data array

    

• Serial

  • Pipelining cache access

  • First check for tag hit, then in second step access the correct cache line

  • More latency but less energy, no multiplexer

    

• Comparison:
  • Serial good enough for Out-Of-Order Execution since OOO-Processors hide latency
  • Parallel for In-Order Execution

Avoiding Address Translation #

• Use virtual addresses in the cache
• remove TLB from the critical path

Way prediction #

• Predict the cache line in a Set-associative cache
• Fast if predicted correctly (similar to Direct mapped cache )
• If predicted wrong, then slower than normal set associative cache