Unified Issue Queue

A way to implement Out-Of-Order Execution .

• A bit similar to Tomasulo Algorithm but only have a single issue queue.

• Per instruction store:

  • Ctrl info: operation, required ALU, data size, …
  • Per operand store
    • SrcId: operand identifier generated by Renaming / Allocation stage .
    • Valid: if operand is used (some instructions might not use all operands)
    • Ready: data is available

• Each operation result is then propagated back through the content addressable memory (“CAM”) to look for instructions waiting for the result and filling in the missing operands