| Lecture 1+2 |
Computer History
|
| Lecture 3 |
Crosscutting Aspects
|
| Lecture 4 |
Instruction Set Architecture
|
| Lecture 5 |
Instruction Pipelining
|
| Lecture 6 |
Branch Prediction
|
| Lecture 7 |
Extended Instruction Pipeline
, Instruction Fetch
, Instruction Decode
|
| Lecture 8 |
Issue Stage
|
| Lecture 9 |
Memory Disambiguation
, Execution Stage
, Bypass Network
|
| Lecture 10 |
Commit Stage
, Compiler support for preventing stall cycles
|
| Lecture 11 |
Intel Knights Landing (KNL)
, CPU Caches
|
| Lecture 12 |
Cache Optimizations
|
| Lecture 13 |
Cache Optimizations
|
| Lecture 14 |
Prefetching
, Volatile Memory
|
| Lecture 15 |
Virtual Memory
, Non-Volatile Memory
|
| Lecture 16 |
Very Long Instruction Word (VLIW) processing
|
| Lecture 17 |
GPGPU and Multithreading |
| Lecture 18 |
SIMD
|
| Lecture 19 |
Shared Memory |
| Lecture 20 |
Consistency and Synchronization |
| Lecture 21 |
Chip Multiprocessors and NUMA |
| Lecture 22 |
Networks |
| Lecture 23 |
Top500 and SuperMUC |